FPU / SSE / SSE2 / SSE3 / SSSE3 (etc)
optimization
vs
FPU / MMX / SSE

As a screensaver is coming, and the core science application will have to be optimized (at least at the command line interface of the compiler) for SSE and beyond yet again.

The SSE optimization so far has paid off, but more experimentation and tries at SSE3 and SSSE3 should be tried.

I don't know about user uptake of SSE4 or SSE5 at this time. As for the other more advanced instructions, one will have to wait.

I would almost expect Intel to totally dump MMX in the future -- there is not an infinite amount of room for all the logic gates.